Fabrication of dual gate oxides in semiconductor devices requires several steps when thin and thick gate oxides are desired. These steps add time and cost in the fabrication of the semiconductor devices.
The "Electrical Characteristics of High-Quality Sub-25-.ANG. Oxides Grown by Ultraviolet Ozone Exposure at Low Temperature;" Electron Device Letters, March, 1999, pp 132-134, G. D. Wilk and B. Brar; Publisher Item Identifier S 0741-3106/9510270-2, discusses a UVO.sub.3 (ultraviolet ozone) oxidation method for controllably and reproducibly growing self-limiting ultrathin oxides from .about.10-25 .ANG. thick with excellent electrical properties at temperatures from 25.degree. C. to 600.degree. C., respectively. The self-limiting thickness depending primarily on the substrate temperature and the oxides so grown have comparable electrical quality to thermal oxides with similar leakage current densities and breakdown fields.
U.S. Pat. No. 5,880,029 to Eisenbeiser et al. describes a method of passivating semiconductor devices by exposing the surface of the semiconductor devices to deep ultraviolet (DUV) radiation, in an atmosphere including O.sub.2, forming a layer of oxide (SiO.sub.2) on the surface of the semiconductor material and forming a layer of passivation material on the layer of oxide.
U.S. Pat. No. 5,698,472 to Harris describes a method and device for oxidation of a semiconductor surface layer of SiC to form an insulating surface layer of SiO.sub.2. The SiO.sub.2 layer is formed by heating the semiconductor layer, feeding O.sub.2 to the semiconductor layer which diffuses therein and reacts with the SiC to form C-oxides that diffuse out of the semiconductor layer and to form SiO.sub.2, and illuminating it with vacuum ultraviolet light during at least a phase of the oxidation to improve the quality of the SiO.sub.2 layer.
U.S. Pat. No. 4,474,829 to Peters describes a process for forming a layer of a native oxide on a semiconductor substrate surface by exposing a chosen oxygen-containing precursor over the substrate to radiation to form only charge-free atomic oxygen that in turn is the primary oxidizing species to form the native SiO.sub.2 layer over the substrate.
U.S. Pat. No. 5,863,819 to Gonzalez describes a method of fabricating a DRAM access transistor with a dual gate oxide technique. Beginning with a substrate on which a local oxidation of silicon process has been performed, the process comprises: stripping a pad oxide layer and growing a sacrificial oxide layer; masking the sacrificial oxide layer with a photoresist to protect the memory array area; stripping the unmasked sacrificial oxide; stripping the photoresist; and growing a gate oxide layer which is thinner than the sacrificial oxide layer. Thereafter, the memory device fabrication may be completed using any known prior art techniques.